DDR5 Ram Explained
DDR5 Ram (Double Data Rate 5 Synchronous Dynamic Random-Access Memory) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 is planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on 14 July 2020. A new feature called Decision Feedback Equalization (DFE) enables IO speed scalability for higher bandwidth and performance improvement. DDR5 supports more bandwidth than its predecessor, DDR4, with 4.8 gigabits per second possible — but not shipping at launch. DDR5 will have about the same latency as DDR4 and DDR3.
Rambus announced a working DDR5 DIMM in September 2017. On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; it runs at 5200 MT/s at 1.1 V. In February 2019, SK Hynix announced a 6400 MT/s chip, the highest speed officially allowed by the preliminary DDR5 standard. Some companies were planning to bring the first products to market by the end of 2019. The world’s first DDR5 DRAM chip was officially launched by SK Hynix on October 6th, 2020.
DDR4 and DDR5 Ram
Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules can incorporate on-board voltage regulators in order to reach higher speeds; but as this will increase cost, it is expected to be implemented only on server-grade and possibly high-end consumer modules. DDR5 supports a speed of 51.2 GB/s per module and 2 memory channels per module.
There is a general expectation that most use-cases that currently use DDR4 will eventually migrate to DDR5. To be usable in desktops and servers (laptops will presumably use LP-DDR5 instead), the integrated memory controllers of e.g. Intel’s and AMD’s CPUs will have to support it; as of June 2020, there have not been any official announcements of support from either. Intel’s 11th-gen Rocket Lake CPUs and AMD’s Ryzen 5000-series CPUs both still use DDR4 RAM. A leaked internal AMD roadmap is reported to show DDR5 support for 2022 Zen 4 CPUs and Zen 3+ APUs. A leaked slide shows planned DDR5 support on Intel’s 2021 Sapphire Rapids microarchitecture and Alder Lake microarchitecture. To purchase the best DDR5 Ram, check the link below:
Advantages and Benefits of DDR5 Ram
Highest capacity in optimistic storage
A sixth and final change to highlight is DDR5’s support for higher capacity DRAM devices. With DDR5 buffer chip DIMMs, the server or system designer can use densities of up to 64 Gb DRAMs in a single-die package. DDR4 maxes out at 16 Gb DRAM in a single-die package (SDP). DDR5 supports features like on-die ECC, error transparency mode, post-package repair, and read and write CRC modes to support higher-capacity DRAMs. The impact of higher capacity devices obviously translates to higher capacity DIMMs. So, while DDR4 DIMMs can have capacities of up to 64 GB (using SDP), DDR5 SDP-based DIMMs quadruple that to 256 GB.
Challenging Design of DDR5 Ram
For DDR4 designs, the primary signal integrity challenges were on the dual-data-rate DQ bus, with less attention paid to the lower-speed command address (CA) bus. For DDR5 designs, even the CA bus will require special attention for signal integrity. In DDR4, there was consideration for using differential feedback equalization (DFE) to improve the DQ data channel. But for DDR5, the RCD’s CA bus receivers will also require DFE options to ensure good signal reception. The power delivery network (PDN) on the motherboard is another consideration, including up to the DIMM with the PMIC.
Considering the higher clock and data rates, you will want to make sure that the PDN can handle the load of running at higher speed, with good signal integrity, and with good clean power supplies to the DIMMs. The DIMM connectors from the motherboard to the DIMM will also have to handle the new clock and data rates. For the system designer, at the higher clock speeds and data rates around the printed circuit board (PCB), more emphasis must be placed on system design for electromagnetic interference and compatibility (EMI and EMC).
Memory interface chips
The good news is that DDR5 memory interface chips improve signal integrity for the command and address signals sent from the host memory controller to the DIMMs. The bus for each of the two channels goes to the RCD and then fans out to the two halves of the DIMM. The RCD effectively reduces the loading on the CA bus that the host memory controller sees. DDR5 data buffer chips will reduce the effective load on the data bus, enabling the higher-capacity DRAMs on the DIMM without degrading latency. Rambus offers a DDR5 memory interface chipset that helps designers harness the full advantages of DDR5 while dealing with the signal integrity challenges of higher data, CA and clock speeds.
Longer Burst Length
The fifth major change is burst length. DDR4 burst chop length is four and burst length is eight. For DDR5, burst chop and burst length will be extended to eight and sixteen to increase burst payload. Burst length of sixteen (BL16), allows a single burst to access 64 Bytes of data, which is the typical CPU cache line size. It can do this using only one of the two independent channels. This provides a significant improvement in concurrency and with two channels, greater memory efficiency.
The archtecture of DDR5 and DDR4 Ram
Another major change with DDR5, number four on our list, is a new DIMM channel architecture. DDR4 DIMMs have a 72-bit bus, comprised of 64 data bits plus eight ECC bits. With DDR5, each DIMM will have two channels. Each of these channels will be 40-bits wide: 32 data bits with eight ECC bits. While the data width is the same (64-bits total) having two smaller independent channels improves memory access efficiency. So not only do you get the benefit of the speed bump with DDR5, the benefit of that higher MT/s is amplified by greater efficiency.
In the DDR5 DIMM architecture, the left and right side of the DIMM, each served by an independent 40-bit wide channel, share the RCD. In DDR4, the RCD provides two output clocks per side. DDR5, the RCD provides four output clocks per side. In the highest density DIMMs with x4 DRAMs, this allows each group of 5 DRAMs (single rank, half-channel) to receive its own independent clock. Giving each rank and half-channel an independent clock improves signal integrity, helping to address the lower noise margin issue raised by lowering the VDD.
The difference that makes the powerful DDR5
A third change, and a major one, is power architecture. With DDR5 DIMMs, power management moves from the motherboard to the DIMM itself. DDR5 DIMMs will have a 12-V power management IC (PMIC) on DIMM allowing for better granularity of system power loading. The PMIC distributes the 1.1 V VDD supply, helping with signal integrity and noise with better on-DIMM control of the power supply.
Low Power and Voltage
A second major change is a reduction in operating voltage (VDD), and that will translate to lower power. With DDR5, the DRAM, buffer chip registering clock driver (RCD) and data buffer (DB) voltage drops from 1.2 V down to 1.1 V. However, lower VDD means smaller margin for noise immunity which designers will have to be cognizant of their implementations.
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